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IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
* Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * All inputs, outputs, and I/O are 5V tolerant * Available in SSOP, TSSOP, and TVSOP packages
IDT74LVCH162245A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
* Balanced Output Drivers: 12mA (A port) * High Output Drivers: 24mA (B port)
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
This 16-bit bus transceiver is built using advanced dual metal CMOS technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and Output Enable controls are designed to operate this device as either two independent 8-bit transceivers or one 16-bit transceiver. The direction control pin (DIR) controls the direction of data flow. The output enable pin (OE) overrides the direction control and disables both ports. All inputs are designed with hysteresis for improved noise margin. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCH162245A (B port) has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH162245 (A port) has series resistors in the device output structure which will significantly reduce line noise when used with light loads. The driver has been designed to drive 12mA at the designated threshold levels. The LVCH162245A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1DIR
1 48 24
2DIR
25
1OE 1A1
47 2 46
2OE 2A1
36 13 35
1B1 2A2
2B1
1A2
3
14
1B2 1A3
44 5 33
2B2 2A3
16
1B3 1A4
43 6 32
2B3 2A4
17
1B4
41 30
2B4 2A5
1A5
8
1B5
40
19 29
2B5
1A6
9
2A6 1B6
20 27 22
2B6
1A7
38 11
2A7 1B7
2B7 2A8
26 23
1A8
37 12
1B8
2B8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4597/1
IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND -0.5 to +6.5 -65 to +150 -50 to +50 -50 100 TSTG
1OE 1A1 1A2
Unit V C mA mA mA
1DIR 1B1 1B2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
IOUT IIK IOK ICC ISS
GND
1B3 1B4
GND
1A3 1A4
VCC
1B5 1B6
VCC
1A5 1A6
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GND
1B7 1B8 2B1 2B2
GND
1A7 1A8 2A1 2A2
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
NOTE: 1. As applicable to the device type.
GND
2B3 2B4
GND
2A3 2A4
PIN DESCRIPTION
Pin Names xOE xDIR xAx xBx Description Output Enable Input (Active LOW) Direction Control Output Side A Inputs or 3-State Outputs(1) Side B Inputs or 3-State Outputs(1)
VCC
2B5 2B6
VCC
2A5 2A6
GND
2B7 2B8 2DIR
GND
2A7 2A8 2OE
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE (EACH 8-BIT SECTION)(1)
Inputs xOE xDIR L H X Outputs B Data to A Bus A Data to B Bus High Z State
SSOP/ TSSOP/ TVSOP TOP VIEW
L L H
NOTE: 1. H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level Z = High-Impedance
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IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- -- -- -0.7 100 -- -- -- 50 -1.2 -- 10 10 500 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND
A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 -- -- --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
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IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS (A PORT)
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 4mA IOH = - 6mA IOH = - 4mA IOH = - 8mA IOH = - 6mA IOH = - 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC - 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS (B PORT)
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
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IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per Transceiver Outputs enabled Power Dissipation Capacitance per Transceiver Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 39 4 Unit pF
SWITCHING CHARACTERISTICS (A PORT)(1)
Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xBx to xAx Output Enable Time xOE to xAx Output Disable Time xOE to xAx Output Skew(2) Min. 1.5 1.5 1.5 VCC = 2.7V Max. 5.7 7.9 8.3 VCC = 3.3V 0.3V Min. Max. 1.5 4.8 1.5 2.2 6.3 7.4 500 Unit ns ns ns ps
--
--
--
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS (B PORT)(1)
Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xAx to xBx Output Enable Time xOE to xBx Output Disable Time xOE to xBx Output Skew(2) Min. 1.5 1.5 1.5 VCC = 2.7V Max. 4.7 6.7 7.1 VCC = 3.3V 0.3V Min. Max. 1 4 1.5 1.5 5.5 6.6 500 Unit ns ns ns ps
--
--
--
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse (1, 2) Generator VIN D.U.T. RT 500 CL
LVC Link
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
6 2.7 1.5 300 300 50
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V
LVC Link
VOUT
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2
LVC Link
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
INPUT
Set-up, Hold, and Release Times
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE VT
LVC Link
tPLH1
tPHL1
OUTPUT 1
VT
tSK (x)
tSK (x)
OUTPUT 2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Pulse Width
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
X LVC IDT XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package
PV PA PF
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package
245A 16-Bit Bus Transceiver 162 Double-Density with Resistors, 24mA (B Port) 12mA (A Port)
H 74
Bus-hold -40C to +85C
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